For a frequency synthesizer used in a communication system, one that can output various frequency signals is required. In particular, as a communicable band is being fragmented, it is necessary that a frequency step of an output can be finely set in the frequency synthesizer. In a frequency synthesizer used in a communication system, it is general to use a PLL (Phase Locked Loop) circuit.
As a PLL circuit, an integer frequency division type PLL circuit (integer-N PLL) in which a frequency division ratio is integer only is generally known. In the integer-N PLL circuit, in order that a frequency division ratio for obtaining an output of a desired frequency becomes integer, a signal with a lower frequency obtained by frequency-dividing a clock signal inputted from the outside is set as a standard signal (reference clock signal). However, when a frequency of the reference clock signal, that is, a comparison frequency related to phase comparison, becomes low, a cut-off frequency of a loop filter (low-pass filter) is also necessary to be reduced. Thus, it is inevitable to increase a capacitance value of a capacitance in the loop filter, thereby increasing a circuit area. Further, a narrowed loop band leads to decrease of a phase noise reduction effect.
As one of methods of preventing lowering of the comparison frequency related to phase comparison as described above, there is suggested a fractional frequency division type PLL circuit called a fractional-N PLL circuit, an example of which is illustrated in FIG. 12. The fractional-N PLL circuit temporally changes an integer frequency division number in a frequency divider. In other words, the fractional-N PLL circuit gives disturbance to a frequency division ratio in relation to a time axis thereby to realize a frequency division ratio including not only an integer but also a fraction (decimal fraction) equivalently and averagely.
FIG. 12 is a diagram illustrating a constitution example of a fractional-N PLL circuit.
In FIG. 12, a reference numeral 101 indicates a phase frequency comparator (PFD), a reference numeral 102 indicates a charge pump circuit (CP), a reference numeral 103 indicates a low-pass filter (LPF), a reference numeral 104 indicates a voltage-controlled oscillator (VCO), a reference numeral 105 indicates a variable frequency divider (DIV), and a reference numeral 106 indicates a ΣΔ modulator (ΣΔ mod).
To the phase frequency comparator 101, a reference clock signal fREF is inputted and a frequency-divided clock signal fDIV outputted from the variable frequency divider 105 is inputted. The phase frequency comparator 101 outputs a pulse signal corresponding to a frequency difference and a phase difference between the reference clock signal fREF and the frequency-divided clock signal fDIV to the charge pump circuit 102. The charge pump circuit 102 outputs an output signal corresponding to the pulse signal outputted from the phase frequency comparator 101 to the low-pass filter 103.
The low-pass filter (loop filter) 103 has resistances Rs, Rr and capacitances Cs, Cp, Cr, as illustrated in FIG. 12. The low-pass filter 103 smoothes an output signal of the charge pump circuit 102 thereby to remove a high frequency component and outputs to the voltage-controlled oscillator 104 as a control voltage. The voltage-controlled oscillator 104 outputs an output clock signal fOUT of a frequency corresponding to an inputted control voltage to the external circuit and outputs to the variable frequency divider 105.
The variable frequency divider 105 frequency-divides the output clock signal fOUT outputted from the voltage-controlled oscillator 104 and outputs a frequency-divided clock signal fDIV. A frequency division ratio of the variable divider 105 is set based on an output of the ΣΔ modulator 106. The ΣΔ modulator 106 outputs setting information related to the frequency division ratio of the variable frequency divider 105 in correspondence with the frequency-divided clock signal fDIV outputted from the variable frequency divider 105.
The fractional-N PLL circuit illustrated in FIG. 12 temporally changes the frequency division ratio (integer frequency division number) of the variable frequency divider 105 based on the output of the ΣΔ modulator 106, and performs a frequency division operation in which an average frequency division ratio includes a fraction. The fractional-N PLL circuit is capable of setting a fractional value as a frequency division ratio (average frequency division ratio), whereby a frequency of a reference clock signal, that is, a comparison frequency related to phase comparison, can be made higher than in a case of using an integer-N PLL circuit. In other words, it becomes possible to obtain an output of a desired frequency without lowering a comparison frequency related to phase comparison, and it becomes possible to reduce a capacitance value of a capacitance in a low-pass filter compared with in an integer-N PLL circuit. Further, as for a loop band, it also becomes possible to maintain a broad band, whereby it becomes possible to maintain a phase noise reduction effect.
However, in the fractional-N PLL circuit illustrated in FIG. 12, a spurious 110 occurs due to a quantization noise caused by an operation of the ΣΔ modulator 106 in the output clock signal fOUT from the voltage-controlled oscillator 104, as illustrated in FIG. 13. In FIG. 13, a solid line indicates a level of the phase noise of the fractional-N PLL circuit, while a dotted line indicates a level in a case of only with the voltage-controlled oscillator.
As a method of suppressing occurrence of the spurious 110 in the output clock signal fOUT as illustrated in FIG. 13, increasing a capacitance value of a capacitance in a low-pass filter in the fractional-N PLL circuit can be considered. However, in order to sufficiently suppress the occurrence of the spurious, a capacitance value nearly equal to that of the integer-N PLL circuit is necessary as a capacitance value of the capacitance in the low-pass filter, and thus an advantage of the fractional-N PLL circuit is impaired.
Further, there is suggested a fractional-N PLL circuit constituted so that a cycle-to-cycle jitter of a fractional-N PLL circuit can be reduced (for example, see Patent Document 1). In this fractional-N PLL circuit, at least one of a phase frequency comparator and a charge pump circuit is constituted so that a generation operation of an output voltage of a loop filter to be outputted to a voltage-controlled oscillator based on a phase difference detection operation between a phase of one pulse in a reference clock signal and a phase of one pulse in a frequency-divided clock signal which is compared with the pulse in the reference clock is performed by a plurality of generation operations having time differences. Then, the generation operation of the output voltage of the loop filter based on a phase difference detection operation between the phase of one pulse in the reference clock signal and the phase of one pulse in the frequency-divided clock signal is performed in a plurality of operations divided by a time axis during the one pulse time period. As stated above, by dividing the generation operation of the output voltage of the loop filter into the plural operations during one pulse time period, an overshoot amount of the output voltage is reduced and the cycle-to-cycle jitter is reduced.
Further, there is suggested a fractional-N PLL circuit which generates, by a frequency divider, a first frequency-divided clock signal and a second frequency-divided clock signal having a predetermined phase relationship by frequency-dividing an oscillation output of a voltage-controlled oscillator, and which controls a control voltage to be supplied to the voltage-controlled oscillator in correspondence with a comparison result of a reference clock signal and the first frequency-divided clock signal as well as a comparison result of the reference clock signal and the second frequency-divided clock signal (for example, see Patent Document 2).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2007-288375
[Patent Document 2] Japanese National Publication of International Patent Application No. 2004-530334